1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory arranged with a memory cell array in which a plurality of electrically reprogrammable memory cells are placed in a matrix form, a method for reading this data and a memory card which is mounted on this type of nonvolatile semiconductor memory.
2. Description of the Related Art
Recently, the demand for small scale large capacity nonvolatile semiconductor memory has increased considerably. Among such devices, a NAND type flash memory which can realize high integration and large capacity when compared to conventional NOR type flash memories is drawing attention.
The NAND type flash memory is comprised of a memory cell array in which a plurality of NAND cell units are placed which are arranged with a plurality of memory cells which are connected in series in a form which shares a source and a drain, a drain side selection transistor which is connected to the drain side of this plurality of memory cells and a source side selection transistor which is connected to the source side of this plurality of memory cells.
In the memory cell array, a plurality of word lines are arranged in rows and a memory cell gate electrode is commonly connected in line in this word line direction. Also, each gate electrode of the source side selection transistors which are aligned in a word line direction, is commonly connected to/by a source side selection gate line. Also, a plurality of bit lines are arranged in rows in a direction which intersects the word line direction and each bit line is connected to a corresponding NAND cell unit via the drain side selection transistor. And, a voltage is applied and a plurality of word lines and a plurality of bit lines are selected and a data read-out control part performs a read-out of data in a plurality of memory cells.
Furthermore, in the case of reading data from a memory cell which is connected to the above stated word line, a nonvolatile semiconductor memory is proposed (for example, Japanese Laid Open Patent 2006-107577) which changes the signal supply order of the above stated source side selection gate line and the drain side selection gate line.